MODELLING AND OPTIMIZATION OF SUBTHRESHOLD LEAKAGE CURRENT IN LOW-POWER, SILICON-BASED, COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES

Abstract

The trend of process scaling for CMOS technology has made subthreshold leakage reduction a growing concern for submicron circuit designers. Power consumption has become a principle design consideration as device sizes decrease and many more devices fit on a single chip. Since switching power is proportional to the square of the supply voltage, V 2dd, new processes are tailored for lower supply voltages. The decrease in Vdd slows down devices, which requires that the threshold voltage, Vth, must be lowered to maintain performance. This reduction of Vth produces the exponential increase of subthreshold leakage currents. This research demonstrates a process used to model and optimize subthreshold leakage current for a CMOS device during its standby mode (OFF-state). The process involves the use of MATHCAD to examine the OFF-state subthreshold leakage current, Isub (OFF), based on variations in the threshold voltage, Vth, the effective transistor channel length, L, and the effective transistor channel width, W. The theoretical work entails simplifying the empirical relationship between the surface inversion potential, φs, the gate-source voltage, Vgs, and the Subthreshold swing coefficient, n. This results in an expression relating the OFF-state subthreshold leakage current, Isub (OFF), the threshold voltage, Vth, the effective transistor channel length, L, and the effective transistor channel width, W. Analyzing the resulting equation using MATHCAD confirms that the OFF-state subthreshold leakage current, Isub (OFF) increases exponentially with a decrease in the threshold voltage, Vth, and linearly with a decrease in the effective transistor channel length, L. The results also show that the OFF-state subthreshold leakage current, Isub (OFF), increases linearly with the effective transistor channel width, W. The optimization process resulted in the values of Vth = 140 mV, L = 28 nm and W= 7 nm which give the desired outcome of greatly reduced OFF-state subthreshold leakage current, Isub (OFF) = 0.125 nA, for a single transistor. Field Programmable Gate Arrays (FPGAs) are one type of chip that could benefit from such subthreshold leakage reduction techniques.